Samsung provides one-stop foundry design environment with the launch of ‘SAFE™ CDP’

Forums General News (General) Samsung provides one-stop foundry design environment with the launch of ‘SAFE™ CDP’

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        #News(General) [ via IoTGroup ]


        Samsung Electronics, a provider in advanced semiconductor technology, announced the launch of ‘Samsung Advanced Foundry Ecosystem (SAFE™) Cloud Design Platform (CDP)’ for fabless customers, in collaboration with Rescale, a provider in high performance computing (HPC) applications in the cloud.
        The key highlight feature of Samsung foundry’s first SAFE™ Cloud Design Platform is that it provides a virtual environment to design chips in the cloud.
        By accessing this platform through the cloud, customers can immediately start designing at anytime and anywhere.
        To maximise customers’ design convenience, SAFE™ CDP supports a very secure design condition that has verified with cloud companies.
        In addition, customers can utilise various Electronic Design Automation (EDA) tools offered by multiple vendors such as Ansys, Cadence, Mentor, a Siemens business and Synopsys.
        Gaonchips, one of Samsung Foundry’s Design Solution Partners, has already tested the SAFE™ CDP on its 14nm automotive project using Cadence’s Innovus Implementation System and has successfully reduced its design run-time by 30% compared to current on-premise execution.
        “We expect that our innovative design platform co-developed in partnership with Rescale will play a crucial role for the fabless industry as it evolves into efficient cloud-based design environment,” says Jae-hong Park, executive vice president of Foundry Design Platform Development at Samsung Electronics.
        “We remain committed to our efforts to bolster the SAFE™ ecosystem and will continue to collaborate with our SAFE™ partners on developing innovative programs that will help deliver ease of use and greater design efficiency for customers.”
        By adopting CDP, customers can reduce the burden of building their own server infrastructure, while flexibly utilising additional computing power required for chip design and verification.


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